symbol max p-channel units v ds v v gs v i dm i ar a e ar mj t j , t stg c thermal characteristics: n-channel and p-channe l symbol device typ ma x n-ch 19 23 c/w n-ch 47 60 c/w r jc n-ch 4.5 6 c/w p-ch 19 23 c/w p-ch 47 60 c/w r jc p-ch 4.5 6 c/w -40 -18 a w -9.4 -12 40 1.3 18 -55 to 175 -55 to 175 power dissipation a t a =25c p dsm t a =70c 2.1 2.1 1.3 maximum junction-to-case b steady-state maximum junction-to-ambient a t 10s r ja maximum junction-to-ambient a steady-state 40 t c =100c power dissipation b t c =25c p d steady-state junction and storage temperature range continuous drain current g t c =25c i d t c =100c repetitive avalanche energy l=0.1mh c w 12.5 25 12.5 absolute maximum ratings t a =25c unless otherwise noted parameter max n-channel -30 20 drain-source voltage 20 gate-source voltage parameter maximum junction-to-ambient a t 10s 30 12 9.4 40 25 avalanche current c pulsed drain current c r ja maximum junction-to-ambient a maximum junction-to-case b steady-state AOD607 n-channel p-channel v ds (v) = 30v -30v i d = 12a (v gs =10v) -12a (v gs = -10v) r ds(on) r ds(on) < 25 m ? (v gs =10v) < 37 m ? (v gs = -10v) < 34 m ? (v gs =4.5v) < 62 m ? (v gs = -4.5v) the AOD607 uses advanced trench technology mosfets to provide excellent r ds(on) and low gate charge. the complementary mosfets may be used in h-bridge, inverters and other applications. g1 s1 g2 s2 n-channel p -channel d1/d2 www.freescale.net.cn 1/9 complementary enhancement general description mode field effect transistor features
symbol min typ max units bv dss 30 v 1 t j =55c 5 i gss 100 na v gs(th) 1.5 1.7 2.5 v i d(on) 40 a 20 25 t j =125c 28 34 27.5 34 m w g fs 25 s v sd 0.75 1 v i s 18 a i sm 40 a c iss 1040 1250 pf c oss 180 pf c rss 110 pf r g 0.7 1.5 w q g (10v) 19.8 25 nc q g (4.5v) 9.8 12.5 nc q gs 2.5 nc q gd 3.5 nc t d(on) 4.5 ns t r 3.9 ns t d(off) 17.4 ns t f 3.2 ns t rr 19 25 ns q rr 8 nc v gs =10v, v ds =15v, i d =12a total gate charge gate drain charge v gs =0v, v ds =15v, f=1mhz switching parameters turn-on rise time turn-off delaytime v gs =10v, v ds =15v, r l =1.25 w , r gen =3 w turn-off fall time turn-on delaytime i s =1a,v gs =0v v ds =5v, i d =12a total gate charge gate source charge gate resistance v gs =0v, v ds =0v, f=1mhz maximum body-diode continuous current input capacitance output capacitance dynamic parameters r ds(on) static drain-source on-resistance forward transconductance diode forward voltage i dss m a gate threshold voltage v ds =v gs i d =250 m a v ds =24v, v gs =0v v ds =0v, v gs = 20v zero gate voltage drain current gate-body leakage current n-channel electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions v gs =4.5v, i d =5a drain-source breakdown voltage on state drain current i d =250 m a, v gs =0v v gs =4.5v, v ds =5v pulsed body-diode current c body diode reverse recovery time body diode reverse recovery charge i f =12a, di/dt=100a/ m s v gs =10v, i d =12a reverse transfer capacitance i f =12a, di/dt=100a/ m s m w a: the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the power dissipation p dsm is based on r q ja and the maximum allowed junction temperature of 15 0c. the value in any given application depends on the user's specific board design, and the maximu m temperature of 175c may be used if the pcb allow s it. b. the power dissipation p d is based on t j(max) =175c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsi nking is used. c: repetitive rating, pulse width limited by juncti on temperature t j(max) =175c. d. the r q ja is the sum of the thermal impedence from junction to case r q jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these tests are performed with the device mounte d on 1 in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the soa curve provides a single pulse rating. g. the maximum current rating is limited by bond-wi res. *this device is guaranteed green after data code 8x 11 (sep 1 st 2008). rev3: oct 2008 www.freescale.net.cn 2/9 AOD607 complementary enhancement mode field effect transistor
n-channel typical electrical and thermal characteri stics 0 5 10 15 20 25 30 0 1 2 3 4 5 v ds (volts) fig 1: on-region characteristics i d (a) v gs =3v 3.5v 4v 4.5v 10v 0 4 8 12 16 20 1.5 2 2.5 3 3.5 4 v gs (volts) figure 2: transfer characteristics i d (a) 10 15 20 25 30 35 0 5 10 15 20 i d (a) figure 3: on-resistance vs. drain current and gate voltage r ds(on) (m w w w w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.0 0.2 0.4 0.6 0.8 1.0 v sd (volts) figure 6: body-diode characteristics i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature normalized on-resistance v gs =10v v gs =4.5v i d =5a 10 20 30 40 50 2 4 6 8 10 v gs (volts) figure 5: on-resistance vs. gate-source voltage r ds(on) (m w w w w ) 25c 125c v ds =5v v gs =4.5v v gs =10v i d =12a 25c 125c i d =12a www.freescale.net.cn 3/9 AOD607 complementary enhancement mode field effect transistor
n-channel typical electrical and thermal characteri stics 0 2 4 6 8 10 0 4 8 12 16 20 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 250 500 750 1000 1250 1500 0 5 10 15 20 25 30 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 10: single pulse power rating junction-to- ambient (note f) power (w) 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 11: normalized maximum transient thermal imp edance z q q q q ja normalized transient thermal resistance c oss c rss 0.1 1.0 10.0 100.0 0.1 1 10 100 v ds (volts) i d (amps) figure 9: maximum forward biased safe operating area (note f) 100 m s 10ms 1ms 0.1s 1s 10s dc r ds(on) limited t j(max) =150c t a =25c v ds =15v i d =12a single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja r q ja =60c/w t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t j(max) =150c t a =25c 10 m s www.freescale.net.cn 4/9 AOD607 complementary enhancement mode field effect transistor
symbol min typ max units bv dss -30 v -0.003 -1 t j =55c -5 i gss 100 na v gs(th) -1.5 -2 -2.4 v i d(on) -40 a 30 37 t j =125c 42 50 50 62 m w g fs 17 s v sd -0.76 -1 v i s -18 a i sm -40 a c iss 920 1100 pf c oss 190 pf c rss 122 pf r g 3.6 5 w q g (10v) 18.7 23 nc q g (4.5v) 9.7 11.7 nc q gs 2.54 nc q gd 5.4 nc t d(on) 9 13 ns t r 25 35 ns t d(off) 20 30 ns t f 12 18 ns t rr 21.4 26 ns q rr 13 16 nc body diode reverse recovery time body diode reverse recovery charge i f =-12a, di/dt=100a/ m s drain-source breakdown voltage on state drain current i d =-250 m a, v gs =0v v gs =-10v, v ds =-5v v gs =-10v, i d =-12a reverse transfer capacitance i f =-12a, di/dt=100a/ m s p-channel electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions i dss m a gate threshold voltage v ds =v gs i d =-250 m a v ds =-24v, v gs =0v v ds =0v, v gs =20v zero gate voltage drain current gate-body leakage current r ds(on) static drain-source on-resistance forward transconductance diode forward voltage m w v gs =-4.5v, i d =-5a i s =-1a,v gs =0v v ds =-5v, i d =-12a turn-on rise time turn-off delaytime v gs =-10v, v ds =-15v, r l =1.25 w , r gen =3 w gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time switching parameters total gate charge (4.5v) gate source charge maximum body-diode continuous current input capacitance output capacitance turn-on delaytime dynamic parameters v gs =0v, v ds =-15v, f=1mhz gate drain charge total gate charge (10v) v gs =-10v, v ds =-15v, i d =-12a pulsed body-diode current c a: the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the power dissipation p dsm is based on steady-state r q ja and the maximum allowed junction temperature of 15 0c. the value in any given application depends on the user's specific board de sign, and the maximum temperature fo 175c may be u sed if the pcb or heatsink allows it. b. the power dissipation p d is based on t j(max) =175c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsi nking is used. it is used to determine the current rating, when this rating falls below the package limit. c: repetitive rating, pulse width limited by juncti on temperature t j(max) =175c. d. the r q ja is the sum of the thermal impedence from junction to case r q jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these tests are performed with the device mounte d on 1 in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the soa curve provides a single pulse rating. g. the maximum current rating is limited by the pac kage current capability. *this device is guaranteed green after data code 8x 11 (sep 1 st 2008). rev 3 : oct . 2008 www.freescale.net.cn 5/9 AOD607 complementary enhancement mode field effect transistor
p-channel typical electrical and thermal characteri stics 0 5 10 15 20 25 30 0 1 2 3 4 5 -v ds (volts) fig 1: on-region characteristics -i d (a) v gs =-3v -6v -3.5v -4v -10v 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -v gs (volts) figure 2: transfer characteristics -i d (a) 10 20 30 40 50 60 70 80 0 5 10 15 20 25 -i d (a) figure 3: on-resistance vs. drain current and gate voltage r ds(on) (m w w w w ) 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.0 0.2 0.4 0.6 0.8 1.0 -v sd (volts) figure 6: body-diode characteristics -i s (a) 25c 125c 0.80 1.00 1.20 1.40 1.60 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature normalized on-resistance v gs =-10v v gs =-4.5v 0 10 20 30 40 50 60 70 80 90 100 3 4 5 6 7 8 9 10 -v gs (volts) figure 5: on-resistance vs. gate-source voltage r ds(on) (m w w w w ) 25c 125c v ds =-5v v gs =-4.5v v gs =-10v 25c 125c i d =-12a -4.5v -5v i d =-5a i d =-12a www.freescale.net.cn 6/9 AOD607 complementary enhancement mode field effect transistor
p-channel typical electrical and thermal characteri stics 0 2 4 6 8 10 0 4 8 12 16 20 -q g (nc) figure 7: gate-charge characteristics -v gs (volts) 0 250 500 750 1000 1250 1500 0 5 10 15 20 25 30 -v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss 0 10 20 30 40 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 10: single pulse power rating junction-to- ambient (note f) power (w) 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) z q q q q ja normalized transient thermal resistance c oss c rss 0.1 1.0 10.0 100.0 0.1 1 10 100 -v ds (volts) -i d (amps) figure 9: maximum forward biased safe operating area (note f) 100 m s 10ms 1ms 0.1s 1s 10s dc r ds(on) limited t j(max) =150c, t a =25c v ds =-15v i d =-12a single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja r q ja =60c/w t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t j(max) =150c t a =25c 10 m s www.freescale.net.cn 7/9 AOD607 complementary enhancement mode field effect transistor
- + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform ig vgs - + vdc dut l vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f di/dt i rm rr vdd vdd q = - idt t rr - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms vds ar dss 2 e = 1/2 li ar ar www.freescale.net.cn 8/9 AOD607 complementary enhancement mode field effect transistor
vdc ig vds dut vdc vgs vgs qg qgs qgd charge gate charge test circuit & waveform - + - + -10v vdd vgs id vgs rg dut vdc vgs vds id vgs unclamped inductive switching (uis) test circuit & waveforms vds l - + 2 e = 1/2 li ar ar bv dss i ar ig vgs - + vdc dut l vgs isd diode recovery test circuit & waveforms vds - vds + di/dt rm rr vdd vdd q = - idt t rr -isd -vds f -i -i vdc dut vdd vgs vds vgs rl rg resistive switching test circuit & waveforms - + vgs vds t t t t t t 90% 10% r on d(off) f off d(on) www.freescale.net.cn 9/9 AOD607 complementary enhancement mode field effect transistor
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